The overflow flag TF0 of timer T0 of MCS-51 single chip microcomputer, if the full count is after the CPU response interrupt ().
A. Reset by hardware
B. Reset by software
C. Both a and B are OK
D. Random state
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The overflow flag TF1 of timer T1 of MCS-51 single chip microcomputer, if overflow occurs when the count is full, if query mode is used instead of interrupt mode, it should be ().
A. Reset by hardware
B. Reset by software
C. By software in
D. We don’t have to deal with it
In the calculation of the initial count value of 8051 single chip microcomputer, if the maximum count value is m, the m value in mode 1 is ()
A. M= =8192
B. M= =256
C. M= =16
D. M= =65536
When the timers t0 and T1 count the external pulses, the duration of the high level or low level of the input counting pulse shall not be less than one machine cycle. The special function register SCON has nothing to do with timer / counter control.
A. 对
B. 错
When the timers t0 and T1 count the pulses on the external pins, the duration of the high level and the low level of the count pulses should not be less than 2 machine cycles.
A. 对
B. 错