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For a direct-mapped cache design with a 32-bit address, the following bits of theaddress are used to access the cache.Tag Index Offset31–10 9–5 4–01 What is the cache block size (in words)2 How many entries does the cache have?3 What is the ratio between total bits required for such a cache

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In this exercise, we will look at the different ways that capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, P1 and P2.L1 Size L1 MissRate L1HitTimeP1 2KiB 8.0% 0.66 nsP2 4KiB 6.0% 0.90 ns1. Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates?2. What is the Average Memory Access Time for P1 and P2?

Please upload your Lab Report for Experiment 1, The Basic Calculator.NOTE: upload your Word file, and do not input the text!!!

选择一个与课程相关的问题（教材第八章之后理论或现实问题），进行详细解答。

请说出蛋白质凝胶的方法有哪些，至少4种？