The address of the top of stack is stored in _________________.

A. PC
B. Accumulator
C. SP
D. Base Register

Which is not a feature of Pentium .

A. complex and flex addressing
B. abundant instruction set
C. simple format and fixed instruction length
D. strong support to high language

In an instruction, the number of addresses is 2, one address does double duty of_________.

A. a result and the address of next instruction
B. an operand and a result
C. an operand and the address of next instruction
D. two closed operands

Whyis the branch instruction the worst to limit instruction pipeline?

A. the number of its pipeline stages is larger
B. its instruction cycles iscomplex
C. it can invalidate several instruction fetches
D. the number of its pipelines is large

In indirect sub-cycle , CPU must ___________.

A. fetch operand or store result
B. fetch operand’s address from memory
C. fetch next instruction from memory
D. nothing

In MESI protocol, a read missoccursin the local cache.The beginning state: initial is invalid,snoopy is exclusive. After initiating CPUreadthe data, theendingstateis.

A. initial is exclusive, snoopy is invalid
B. initial is shared, snoopy is shared
C. initial is modified, snoopy is shared
D. initial is modified, snoopy is invalid

is not in SMP’sproperties.

A. Using shared memory
B. Using 2 or more same orsimilarprocessors.
C. Using 2-level local caches
D. Using highperformancenetwork-linkage

Inmulti-processor organizations, the method of sharing Memoryis called.

A. loosely coupled
B. cluster
C. tightly coupled
D. symmetric

At the end of__________,the content of MBR is address of operand.

A. indirect sub-cycle
B. fetch sub-cycle
C. execute sub-cycle
D. interrupt sub-cycle

In multi-processor systems, MESI protocol is used to solve the problem of cache coherence. With Read Miss, when the snoopings have invalidate data, please fill best answers into following table.